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Fine Pitch Die-to-Wafer Hybrid Bonding

RESEARCH PAPER

IEEE ECTC

May 7, 2023

Laura Mirkarimi, Thomas Workman, Jeremy Theil, Gill Fountain, KM Bang, Oliver Zhao, Bongsub Lee, Cyprian Uzoh, Dominik Suwito, Gulian Gao

On behalf of the Program and Executive Committee, it is my pleasure to invite you to IEEE’s 73rd Electronic Components and Technology Conference (ECTC), which will be held at JW Marriott Orlando, Grande Lakes, Orlando, Florida from May 30 to June 2, 2023.

Hybrid Bonding for Chiplet Integration

RESEARCH PAPER

Chiplet Summit 2023

March 18, 2023

Heterogeneous Integration in the AI Era Subi Kengeri, VP AI System Solutions, Applied Materials

Recent advances and trends in Cu-Cu Hybrid Bonding IEEE

RESEARCH PAPER

IEEE

March 11, 2023

John H Lau

Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications

RESEARCH PAPER

IEEE ECTC

June 4, 2022

G. Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, T. Workman, C. Uzoh, B. Lee, KM Bang, G. Guevara

The Direct Bond Interconnect (DBI®) Ultra technology, a die-to-wafer (D2W) and die-to-die (D2D) hybrid bonding, is a platform technology that offers a hermetically sealed solid Cu-Cu interconnect through room temperature bonding and low temperature anneal. DBI wafer to wafer (W2W) bonding has been in high volume production since 2015.

The Influence of Microstructure on Thermal Budget in Hybrid Bonding

Research Paper

IEEE ECTC

May 6, 2022

L. Mirkarimi, C. Uzoh, D. Suwito, G. Fountain, T. Workman, B. Lee, J. Theil, G. Gao,

Advanced package modules built with a hybrid bonding technology offer enhanced thermal performance, reliability, and scalability with the Cu-Cu interconnect. Direct Bond Interconnect (DBI®) Ultra technology is a die-to-wafer (D2W) or die-to-die (D2D) high volume manufacturing compatible process that offers handling die on tape, assembly at room temperature, and low temperature interconnect formation.

Analysis of Die Edge Bond Pads in Hybrid Bonded Multi-Die Stacks

Research Paper

IEEE

May 1, 2022

J. A. Theil, T. Workman, D. Suwito, L. Mirkarimi, G. Fountain, KM Bang, G. Gao, B. Lee, P. Mrozek, C. Uzoh, M. Huynh, and O. Zhao

Direct Bond Interconnect (DBI®) is a hybrid bonding technique that is currently being adopted in the semiconductor industry due to its versatility at enabling zero standoff bonding. It is used in a large segment of products such as Back Side Illuminated (BSI) CMOS image sensors and starting to appear in other applications including 3DNAND.

HVM CMP Process Development for Advanced Direct Bond Interconnect (DBI)

Research Paper

International Conference on Planarization Technologies

January 6, 2022

C. Rudolph, H. Wachsmuth, P. Gansauer, T. Werner, M. Junhaehnel, G. Fountain, J. Theil, L. Mirkarimi,

Direct bonding is a spontaneous dielectric-to-dielectric bond at room temperature with a metal-to-metal connection (here Cu-to-Cu bond) by a low temperature batch annealing process (200°C – 300°C). Therefore, the direct bonding process is attractive for heterogeneous integration and has several advantages over the micro bump bonding with solder [1, 2]. Furthermore, the interconnect density and scaling of interconnects is less limited for this metal cap free bonding process.

Die to Wafer Hybrid Bonding and Fine Pitch Considerations

RESEARCH PAPER

IEEE ECTC

June 15, 2021

Thomas Workman, Laura Mirkarimi, Jeremy Theil, Gill Fountain, KM Bang, Bongsub Lee, Cyprian Uzoh, Dominik Suwito, Guilian Gao, Pawel Mrozek

Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at <; 35 μm pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability.

Die to Wafer Hybrid Bonding and Fine Pitch Considerations

RESEARCH PAPER

IEEE ECTC

June 14, 2021

T. Workman, L. Mirkarimi, J. Theil, G. Fountain, KM Bang, B. Lee, C. Uzoh, D. Suwito, G. Gao, and P. Mrozek

Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at <; 35 μm pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability.

Low Temperature Hybrid Bonding for Die to Wafer Stacking Applications

RESEARCH PAPER

IEEE ECTC

June 12, 2021

G. Gao, L. Mirkarimi, G. Fountain, D. Suwito, J. Theil, T. Workman, C. Uzoh, G. Guevara, B. Lee, M. Huynh, and P. Mrozek

The direct bond interconnect (DBI®) technology is a platform technology that offers a hermetically sealed hybrid bond with solid metal-metal (Cu-Cu is the most common) interconnect at a relatively low thermal budget. The Xperi wafer to wafer hybrid bonding technology has been in high volume production since 2015.

Chemistry and process considerations for the removal of residues for hybrid bonding

RESEARCH PAPER

IMAPS

April 22, 2021

Phillip Tyler, Ian Cochran, Jonathan Fijal, and John Taddei (Veeco Instruments), Thomas Workman, Dominik Suwito, Guilian Gao, Gabe Guevara, Gill Fountain, Cyprian Uzoh, Jeremy Theil, and Laura Mirkarimi (Xperi Corporation)

The 17th Annual Device Packaging Conference (DPC 2021) will be held as an online global event, from April 12-15, 2021. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS).

Die to Wafer Stacking with Low Temperature Hybrid Bonding

RESEARCH PAPER

IEEE

June 5, 2020

G. Gao, L. Mirkarimi, G. Fountain, T. Workman, J. Theil, G. Guevara, C. Uzoh, D. Suwito, B. Lee, K. M. Bang, R. Katkar

The direct bond interconnect (DBI®) Ultra technology, a low-temperature die-to-wafer (D2W) and die-to-die (D2D) hybrid bond, is a platform technology to reliably achieve submicron interconnect pitches. A reliable D2W and D2D assembly with submicron pitch capability will enable widespread disaggregation and chiplet architecture innovation.

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